This invention relates to a nonvolatile semiconductor memory device having a CMOS (Complementary Metal Oxide Semiconductor) circuit in a peripheral circuit and, in particular, to a nonvolatile semiconductor memory device having a bias circuit for clamping a potential on a bit line down to below a power supply potential.
A bias circuit is provided for a memory device, such as an EPROM (electronically programmable read-only memory) or an E.sup.2 to clamp a power supply potential so that an excessive voltage cannot be applied to the drain of a transistor constituting a memory cell. Through the bias circuit a relatively low bias voltage is applied to the drain of the transistor in the memory to reduce a stress on the memory cell upon the reading-out of the corresponding data and thus to prevent data from being erroneously written into that memory cell.
FIG. 1 is a circuit diagram showing a conventional EPROM of a type in which data can be erased through irradiation with an ultraviolet ray. In FIG. 1, MOS transistor 11 in a memory is of such a type as to have a floating gate and control gate. Writing a "1" or "0" level data into transistor 11 is achieved by setting the threshold voltage to a predetermined level with or without the injection of electrons into the floating gate, respectively. That is, where the "1" level data is written into transistor 11, the threshold voltage is raised through the injection of electrons into the floating gate and where the "0" level data is written into transistor 11, the threshold voltage is left as it is without injecting electrons into the floating gate.
The control gate of transistor 11 is connected to corresponding word line 13, which in turn is connected to the output of the row decoder 12. Transistor 11 is connected at its drain to corresponding bit line 14, which in turn is connected to data sensing node 16 through MOS transistor 15 for column selection.
Bias circuit 40 is connected to node 16. With the device in an operative state a chip enabling signal CE becomes "0" potential level (ground potential level Vss). As a result, p-channel MOS transistor 41 is rendered conductive and n-channel MOS transistor 42 is rendered nonconductive. With the power supply voltage set to be, for example, 5 V, a voltage of about 2.5 V corresponding to the threshold voltage occurs in n-channel MOS transistor 43. A voltage drop of about 1.7 V corresponding to the threshold voltage is produced in n-channel MOS transistors 44 and 45. The threshold voltages of transistors 43, 44 and 45 are set to be, for example, 0.8 V, with their source potential at "0" volt, provided that no substrate bias is applied. Since, however, the source potential of transistor 43 becomes relatively high, that threshold voltage becomes about 2.5 V under a greater substrate bias. On the other hand, the source potential of transistor 44 or 45 becomes relatively low and thus the substrate bias becomes smaller, so that the threshold voltage comes to about 1.7 V. For this reason, transistors 43 and 44, or 43 and 45, undergo a voltage drop of about 4.2 V in total and a voltage of 0.8 V (5.0 V-4.2 V=0.8 V) at best appears on node 16.
Transistor 46 is of an n channel MOS type for permitting current to flow through transistor 43. Transistor 47 is a load element comprised of a normally ON p-channel MOS transistor. In the aforementioned memory device, a potential applied to the drain of transistor 11 is dropped through the utilization of the threshold voltage containing a substrate bias at transistors 43 and 44 as well as the threshold voltage containing the substrate bias at transistors 43 and 45. The threshold voltages of transistors 43, 44 and 45 are set to be a desired level by normally controlling an amount of boron (B) ions to be injected into the channel region of the respective transistor. For this reason, where during the manufacture the amount of ions injected has been varied owing to a variation in parameters, the transistor undergoes a greater variation in threshold voltage due to a greater substrate bias, resulting in a greater potential variation at node 16. The conventional memory device, therefore, is smaller in process margin from the standpoint of manufacture, posing an operational problem.